The present invention relates generally to semiconductor memory devices, and, more particularly, to static random access memory cells.
It is a continuing effort to make semiconductor integrated circuit memory devices ever smaller to consume even lower power. Semiconductor memory devices include, for example, static random access memory, or SRAM, and dynamic random access memory, or DRAM. DRAM memory cells have only one transistor and one capacitor, so they provide a high degree of integration. But DRAM requires constant refreshing, its power consumption and slow speed limit its use to mainly computer main memories. SRAM cell, on the other hand, is bi-stable, meaning it can maintain its state indefinitely as long as adequate power is supplied. SRAM can operate at higher speeds and lower power dissipation, so computer cache memories use exclusively SRAMs. Other applications include embedded memories and networking equipment memories.
One well-known conventional structure of a SRAM cell is a six transistor (6T) cell that comprises six MOS transistors. Briefly, a 6T SRAM cell comprises two cross-coupled inverters that form a latch circuit, i.e., one inverter's output connected to the other inverter's input. The latch circuit is connected between power and ground. Each inverter comprises a NMOS pull-down transistor and a PMOS pull-up transistor. The inverter's outputs serve as two storage nodes, when one is pulled low, the other is pulled high. A complementary bit-line pair is coupled to the pair of storage nodes via a pair of pass-gate transistors, respectively. The gate terminals of the pass-gate transistors are commonly connected to a word-line. When the word-line voltage is switched to a high voltage system, or Vcc, the pass-gate transistors are turned on to allow the storage nodes to be accessible by the bit-line pair. When the word-line voltage is switched to a system low voltage, or Vss, the pass-gate transistors are turned off and the storage nodes are essentially isolated from the bit lines, although some leakage can occur. Nevertheless, as long as the Vcc is maintained above a threshold, the state of the storage nodes is maintained indefinitely.
In a drive to reduce the transistor count in the SRAM cell, a polysilicon-load-4T cell structure is widely used in some older technologies. This structure is to use two polysilicon resistors of very high resistance to replace the two pull-up PMOS transistors in the aforementioned 6T cell. Here the polysilicon resistor pulls up a storage node via a resistor limited current, in lieu of the switched-on PMOS transistor in the 6T cell. But at the low voltage storage node of a 4T structure, a current continuously flows through the turned-on NMOS transistor and the polysilicon resistor, which results in a higher power consumption and lower access speed.
Accordingly, there is a need for an improved SRAM design with various advantages such as low power consumption and reduced leakages.